Abstract:
Every year, the best of engineering talent comes together in academia for Hot Chips conference, to present the best system designs. During Hot Chips 24, Session 9 - the SPARC T5 was presented by Sebastian Turullols and Ram Sivaramakrishnan from Oracle on Wednesday, August 29, 2012. This processor was released 6 months later, by Oracle with their T5 systems on Tuesday March 26, 2013.
Video Presentation:
The video presentation of Session 9 was conducted by Fujitsu, Oracle, and IBM. The middle portion of the presentation, starting at 30 minutes, includes the Oracle presenters.
Slide Presentation:
The following screen shots were taken of the presentation. The full presentation is available here.
[4x memory controllers are capable of a peak of 128 GigaBytes per Second]
[Acceleration of Contended Locks; linked list of address requests; all requests satisfied atomically]
[Directory based level 3 indices, tracked up to 8 sockets on an on-chip SRAM]
[7 links with 14 lanes per link between sockets]
[C2C is a sharing cache]
[28 GigaBytes bandwidth between nodes; allows for aggregation of throughput via intermediate node]
[OLTP workload is extremely shared, makes workloads very difficult to scale]
[Elastic Mode includes all of the power saving features automatically]
[Solaris makes frequency request from hypervisor; cores reduced or cycle skipping used]
[Frequency and Voltage pushes performance maximum possible by the system]
Question-Answer Session: The following information was provided during the Question-Answer session, from the audience.
Voltage required for 3.6GHz varies from part to part. 0.95-1v is needed.
There is one voltage supply for all cores; one common PLL for the entire chip. Cycle skipping is used to vary cycle rate.
Low latency clustering port leverages "Allocated DMA Feature"
T5 no longer has an integrated 10 Gigabie Ethernet Controller.
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